The present invention relates to techniques for eliminating clock feedthrough (charge injection) in MOS FET switched capacitor amplifier circuits.
A practical problem with MOS FET's is their parasitic capacitances. Unwanted capacitances can affect the FET's ability to perform optimally under certain conditions. These conditions mainly deal with situations where the FET is required to operate with large and fast input changes, i.e., during switched operation. The switched capacitor amplifier circuit used widely for Analog-to-Digital (ADCs) conversion is an example. A simplified functional example is shown in FIG. 1A.
As shown in FIG. 1A, the circuit is made up of an inverting amplifier with capacitor (C.sub.f) shunted by a switch. Capacitor C.sub.f provides the output to input feedback required to control the closed loop gain of the amplifier. In bipolar amplifiers such feedback is most likely to be provided by a resistive element. However, in CMOS design a capacitive element is generally preferred. The use of a capacitor in the feedback loop is also the basic building block for a integrator circuit. To keep the capacitor from accumulating a charge or integrating, a switch is placed across the feedback capacitor. This switch periodically dumps the charge across the capacitor. The incoming clock rate is set fast enough to keep the circuit from integrating. As such, a basic closed loop gain stage is created. The basic FET implementation of the switched capacitor amplifier circuit is shown in FIG. 1B. The switched component has been changed to a FET type device. Due to the closeness (separation by a dielectric material) and the size of the elements (gates, drains and sources), the FET transistor exhibits parasitic capacitances that can become a problem in switched applications. This is shown as Cgd (capacitance gate to drain) and Cgs (capacitance gate to source) in FIG. 1B. As long as the switch remains in the open or closed position this capacitance causes negligible circuit performance problems. However when the clock transitions, the charge voltage requirement across the capacitor changes and a small current flows as a result. Generally an equal portion of this current flows in both the source and drain of the switched component (FET 2X). The unwanted effect of this current is known as clock feedthrough or as charge injection. Both terms will be used universally in this discussion.
Given the high FET circuit impedance's, I.sub.parasitic (in the figure) can produce an output error with considerable magnitude (a few tenths of a volt). Such an error may not be acceptable in some applications. Several methods have been devised to deal with clock feedthrough or charge injection as discussed above. Two of these solutions are presented in FIG. 2A and FIG. 2B. FIG. 2A's solution is quite simple. In this scheme an inverted clock is provided to the gate of a second FET identified as 1X. The source and drain of this device are connected together and tied to one side of the 2X FET. When the clock signal to the 2X FET goes low, a charge injection current occurs through the stray capacitance of Cgd. This charge injection results in a current flow toward capacitor C.sub.in. However, at the same time an inverted clock to the 1X FET goes high. The high going signal at the gate of the 1X FET causes a current to flow toward the 1X FET to charge its gate to drain and gate to source stray capacitances. In the process it siphons current that was leaving the 2X FET due to 2X's charge injection. This process therefore provides a cancellation effect through the promotion of opposite charge injections. As the 1X FET uses an inverted version of the same clock, the same clock timing relationship exists for both devices, i.e., both 1X and 2X elements act together simultaneously. The 1X FET could be viewed as a capacitor connected to a voltage that stays in reverse polarity to that of the 2X FET. To be fully functional the 1X FET would have to be designed to subtract or add the same charge injection current as that added or subtracted by the 2X FET, respectively. The major concern is any feedthrough current that appears at the input of the inverting amplifier. Therefore, the 1X FET only needs to address the 2X drain feedthrough current being generated by the 2X gate to drain parasitic capacitance. The parasitic capacitance of a FET is determined mainly by its area. Given that both the source and drain are active in the 1X FET, the 1X FET needs to be one half the area of the 2X FET. In this case the nomenclature 1X and 2X actually reflect the areas of the FETs, i.e., the 1X FET is half as large as the 2X FET.
Another clock feedthrough cancellation method is shown in FIG. 2B. In this scheme a clock of the same phase is fed to two similar inverting stages. The lower stage in the figure is a dummy stage, i.e., it doesn't have a real signal input. Its function is simply to manufacture a second dummy charge injection. The dummy signal and the real signal with its unwanted charge injection are fed to a summing circuit. The signal stage (top) is connected to the positive side of the summer, whereas the dummy charge injection signal is connected to the negative side of the summer. As the same clock is used in both inverters, the same charge injection signal will be generated in each circuit. The dummy's output, however, is seen at the subtractive input of the summer. The dummy output will therefore subtract or cancel the positive clock feedthrough signal. The process has been made overly simple for this presentation. Actually the process can become much more complex. For example, in order to cancel the charge injection completely both the signal and dummy stages must work perfectly together. The traditional method shown in FIG. 2A provides only a coarse cancellation and requires two clocks. It is difficult to obtain the correct ratio of 1X to 2X due to manufacturing process variations. These process variations can result in only partial cancellation of the charge injection or clock feedthrough. Such manufacturing variations can result in cancellation of 70% to 80%. The method shown in FIG. 2B is both difficult and expensive to implement. Not only does it duplicate the basic signal components, but it also requires a relatively complex and expensive summer circuit. The summer can be slow and introduce additional errors such as offset.